My Resume

ALEXANDRA JEANELLE FORSYTHE
LinkedIn: https://www.linkedin.com/in/alexandraforsythe
 
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SKILLS
SoC design, analog circuit design, digital circuit design, Verilog, VHDL, RTL, ASIC, FPGA, Cadence, TCL, Perl, Python, Synopsys, SPICE, MATLAB, Eagle CAD, Altium, DxDesigner, PADS, VLSI, SOC, CMOS, ARM, DSP, embedded systems, UART, C, C++, Java, Linux, Agile, Scrum, Fusion
 
 
WORK EXPERIENCE
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Lockheed Martin Advanced Technology Labs, Research Engineer, Eagan, MN            July 2023 to Present
Developing new solutions in wide-ranging areas such as energy and power, artificial intelligence, robotics, human-machine symbiosis, hypersonics, spectrum operations, and cyber.

Intel Corporation, SoC Design Engineer, Hillsboro, OR                                                May 2019 to July 2023
Key team member for the SoC Structural Design Team and SoC Clock Design Team
  • Owned blocks, performed timing analysis and reviewed power-related issues. Implemented corrections on multiple gated and ungated power domains, and worked on timing and clocking issues within multiple blocks and addressed design errors in RTL. Received Device Development Group’s weekly award for work on block progress.
  • Functioned as front line (pre-placement) expert for 50+ DRC rules checks (SDHC and tCIC checks). Performed Structural Design Health Checks (SDHCs) on various SoC device partitions using APR (Advanced Package Router) tools. Ran Synopsys ICC2 checkers and a proprietary clock simulation tool on physical clock routes on DDR, MEMS, and SoC designs; Fixed issues by correcting layout.
  • Owned 5 front-end to back-end RTL quality checks for SD collateral on all blocks within a subsystem, completed debug and communicated with team and experts to generate fixes. Ran and debugged RTL checks to ensure design quality (cross clock domains (CDC), clocks, reset, latency).
  • Responsible for timing closure of complex multi-voltage partitions integrated in multiple SoC dies, and generated voltage areas, placed macros, and ran Fusion Compiler (synthesis and placement).
  • Used Synopsis tools to debug and fix errors found in floorplan and increase power efficiency.
  • Worked on design with 5 clocks and over 2000 sinks, and on the latest generation Intel technology (below 14nm). Projects involved multiple blocks and areas, and ran across multiple product lines with annual sales of $30B and projected future sales of $36B.
  • Improved team’s troubleshooting ability by designing tool for troubleshooting errors in partitions saving the company over 400 labor hours. 
  • Created multiple scripts in Python, TCL, and Shell to: augment the floorplan quality; check script and the flow file; identify the list of physical ports fanning into and/or out of a given hierarchy; generate a summary of Layout Verification (LV); create placement order of bumps; and generate placement results with special cases and automated bus expansion. Migrated proprietary scripts to create physical routes from Verilog inputs in support of next generation designs.
  • Worked with a 20-member design team to develop next-generation high-performance CPU and SoC designs in sub-micron technologies for the Devices Development Group, including micro-architecture, IP integration, circuit design, STA, APR, timing convergence, power grid, block subsystem FC (full chip) contexts with convergence, and FEV (functional equivalents verification). 
 
Indiana Tech, Adjunct Professor, Fort Wayne, IN                                                  September 2022 to Present
  • Prepare and lead lectures for two courses: Digital Circuits and Electronics I with accompanying labs.
  • Topics include circuit analysis and design, including Karnaugh maps, power requirements, electronic measurements, digital logic gates, tolerance and significant figures, Kirchhoff’s laws, Ohm’s Law, capacitors, inductors, operational amplifiers, Boolean algebra, and binary numbers.
  • Provide instruction and models using pSpice-based simulators, along with an introduction to protoboarding, soldering, and use of multimeter, function generators, and oscilloscopes.
  • Utilize and integrate online teaching systems, and mentor and advise undergraduate students.
 
Ultra Electronics USSI, Electrical Engineer, Columbia City, IN                                 March 2018 to May 2019 
  • Responsible for adding Bluetooth functionality to the controller board of an HS-10.
  • Involved in the design of digital electronics, simulation, fabrication, assembly, testing of designs embedded software, defining the requirements for a new design, developing requirements specification, and modeling, building, testing, and modifying product prototypes using working models or theoretical models constructed with simulation.
  • Engineered schematics and generated Gerber files for PCB fabrication. 
  • Peer reviewed schematic and board layout; revised schematics and ran board level design rule checks (DRC). 
  • Demonstrated knowledge of clock distribution, industry standard circuit and design tools, timing and electrical analysis of circuits, and schematic capture. 
 
Raytheon, Electrical and Computer Engineer, Fort Wayne, IN                                May 2018 to August 2018
  • Developed dynamic software with multi-state team for a $12M autonomous collaborative system that uses artificial neural networks to enable UAVs (unmanned aerial vehicles) to work together to accomplish tasks and utilize the unique strength of each UAV. 
  • Created documentation and helped with guidelines and specifications.
  • Utilized scripting to support efficient handling of data, and programmed in C++ for hardware modeling, testbench development, and projects of similar scope and complexity.
 
NASA Langley, Electrical Engineer, Hampton, VA                                                    May 2017 to August 2017
  • Designed an analog mission-critical circuit board for use on a $2.2B lander. 
  • Evaluated design architectures for a DC-DC buck converter for Navigation Doppler Lidar (NDL). 
  • Created designs to meet aggressive power, performance, and area targets. 
  • Performed HW modeling and simulations using design and simulation tools including Webench (SPICE - based simulator) and Altium to test and improve microarchitecture designs. 
  • Developed project documentation including specifications, schematic diagrams, PCB layouts, schedules and presentations to fully capture and communicate the electrical design to achieve the projects’ goals.
  • Participated in design reviews, layout verification, and timing and electrical analysis of circuits. 
 
Forsythe Engineering, Systems Engineer, Huntington, IN                                 October 2016 to August 2021
  • Design, build, and manage complex systems including software, hardware, and mechanical.
  • Engage in all phases of new product introduction: concept, architecture, documentation, design, prototype, sales, marketing, scheduling, and management. 
  • Utilize MATLAB, LT Spice, SPICE, Cadence, Eagle CAD, DxDesigner, and other simulation/modeling tools to design and sell custom circuit boards across the country; over 150 units (over $7500) sold.  
  • Develop, design, and implement electrical solutions for consumer electronic products, including but not limited to schematic capture, part selections, PCB layout, analysis and validation of prototype systems that meet the goals of the product while managing constraints in space, time, cost, performance, power, signal integrity, timing margins, and manufacturing. 
  • Model control loop feedback and signal processing algorithms using MATLAB and Simulink.
  • Worked on all aspects of ASIC integration including floorplanning, clock and power distribution, global signal planning, I/O planning, and hard IP integration.
  • Pioneered projects utilizing tools such as Perl, Python, ASIC, FPGA, SoC (system-on-chip), Linux, RTL design (Verilog and VHDL) and verification (SystemVerilog). Projects included a fully functional R2-D2, SoC for robotics, Raspberry Pi supercomputer (Beowulf), and particle accelerator (CRT).
 

EDUCATION
Master’s Degree in Electrical Engineering and Artificial Intelligence, Penn State. Anticipated graduation 2024. GPA: 4.0/4.0.
B.S. in Electrical Engineering, minor in Math, minor in Computer Science. Indiana Tech. May 2022.
GPA: 4.0/4.0. Summa cum laude. Top student in the College of Engineering.
Indiana Tech Convocation Speaker for a crowd of 4K, August 2021. Study Abroad (Germany). 
Member of accreditation team to ensure continued ABET approval. 
 

LEADERSHIP AND AWARDS
Winner of 12 Intel Corporation Recognition Awards for outstanding work performance (2019 - 2022). National STEM Role Model, National Women in Computing Award, IEEE officer responsible for successfully increasing membership by 400% in one year. CAD Mentor. Peer Mentor.
 
 
COMMUNITY SERVICE
STEM Teacher (Coder Dojo, BeWISE and DoD STARBASE STEM Camps, Tech Engineering Camp).
Member of the Portland Audubon team that exceeded fundraising goals by over 300%. 
Keynote speaker, program developer, editor, and author for several nonprofit organizations since 2012.
 
 
Multiple letters of recommendation on LinkedIn: https://www.linkedin.com/in/alexandraforsythe